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1 features ? provides t1 clock at 1.544 mhz locked to an 8 khz reference clock (frame pulse) ? provides cept clock at 2.048 mhz and st-bus clock and timing signals locked to an internal or external 8 khz reference clock ? typical inherent output jitter (un?ltered)= 0.07 ui peak-to-peak ? typical jitter attenuation at: 10 hz=23 db,100 hz=43 db, 5 to 40 khz 3 64 db ? jitter-free free-run mode ? uncommitted two-input nand gate ? low power cmos technology applications ? synchronization and timing control for t1 and cept digital trunk transmission links ? st- bus clock and frame pulse source description the mt8941b is a dual digital phase-locked loop providing the timing and synchronization signals for the t1 or cept transmission links and the st-bus. the ?rst pll provides the t1 clock (1.544 mhz) synchronized to the input frame pulse at 8 khz. the timing signals for the cept transmission link and the st-bus are provided by the second pll locked to an internal or an external 8 khz frame pulse signal. the mt8941b offers improved jitter performance over the mt8940. the two devices also have some functional differences, which are listed in the section on differences between mt8941b and mt8940. ordering information mt8941be 24 pin plastic dip (600 mil) MT8941BP 28 pin plcc -40 c to +85 c figure 1 - functional block diagram f0i c12i ms0 ms1 ms2 ms3 c8kb c16i ai bi yo v dd v ss rst cvb cv encv f0b c4b c4o enc4o c2o c2o enc2o 2:1 mux variable clock control mode selection logic dpll #2 input selector clock generator frame pulse control 4.096 mhz clock control 2.048 mhz clock control dpll #1 ds5186 issue 1 june 1999 mt8941b advanced t1/cept digital trunk pll cmos st-bus ? family
mt8941b cmos 2 figure 2 - pin connections pin description pin # name description dip plcc 11en cv variable clock enable (ttl compatible input) - this input directly controls the three states of cv (pin 22) under all modes of operation. when high, enables cv and when low, puts it in high impedance condition. it also controls the three states of cvb signal (pin 21) if ms1 is low. when encv is high, the pin cvb is an output and when low, it is in high impedance state. however, if ms1 is high, cvb is always an input. 2 2 ms0 mode select 0 input (ttl compatible) - this input in conjunction with ms1 (pin 4) selects the major mode of operation for both dplls. (refer to tables 1 and 2.) 3 3 c12i 12.352 mhz clock input (ttl compatible) - master clock input for dpll #1. 4 6 ms1 mode select-1 input (ttl compatible) - this input in conjunction with ms0 (pin 2) selects the major mode of operation for both dplls. (refer to tables 1 and 2.) 57 f0i frame pulse input (ttl compatible) - this is the frame pulse input at 8 khz. dpll #1 locks to the falling edge of this input to generate t1 (1.544 mhz) clock. 68 f0b frame pulse bidirectional (ttl compatible input and totem-pole output) - depending on the minor mode selected for dpll #2, it provides the 8 khz frame pulse output or acts as an input to an external frame pulse. 7 9 ms2 mode select-2 input (ttl compatible) - this input in conjunction with ms3 (pin 17) selects the minor mode of operation for dpll #2. (refer to table 3.) 8 10 c16i 16.384 mhz clock input (ttl compatible) - master clock input for dpll #2. 911en c4o enable 4.096 mhz clock (ttl compatible input) - this active high input enables c4o (pin 11) output. when low, the output c4o is in high impedance condition. 10 12 c8kb clock 8 khz bidirectional (ttl compatible input and totem-pole output) - this is the 8 khz input signal on the falling edge of which the dpll #2 locks during its normal mode. when dpll #2 is in single clock mode, this pin outputs an 8 khz internal signal provided by dpll #1 which is also connected internally to dpll #2. 11 13 c4o clock 4.096 mhz (three state output) - this is the inverse of the signal appearing on pin 13 (c4b) at 4.096 mhz and has a rising edge in the frame pulse ( f0b) window. the high impedance state of this output is controlled by enc4o (pin 9). 12 14 v ss ground (0 volt) 28 pin plcc 24 pin pdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 envc ms0 c12i ms1 f0i f0b ms2 c16i enc4o c8kb c4o vss vdd rst cv cvb yo bi ai ms3 enc2o c2o c2o c4b 4 5 6 7 8 9 10 11 25 24 23 22 21 20 19 nc nc cvb yo bi ai ms3 enc2o nc ms1 f0i f0b ms2 c16i enc4o c2o 3 2 1 28 27 26 12 13 14 15 16 17 18 c12i ms0 encv vdd rst cv c8kb c4o vss c4b c2o nc
cmos mt8941b 3 13 15 c4b clock 4.096 mhz- bidirectional (ttl compatible input and totem-pole output) - when the mode select bit ms3 (pin 17) is high, it provides the 4.096 mhz clock output with the falling edge in the frame pulse ( f0b) window. when pin 17 is low, c4b is an input to an external clock at 4.096 mhz. 14 16 c2o clock 2.048 mhz (three state output) - this is the divide by two output of c4b (pin 13) and has a falling edge in the frame pulse ( f0b) window. the high impedance state of this output is controlled by en c2o (pin 16). 15 17 c2o clock 2.048 mhz (three state output) - this is the divide by two output of c4b (pin 13) and has a rising edge in the frame pulse ( f0b) window. the high impedance state of this output is controlled by en c2o (pin 16). 16 19 en c2o enable 2.048 mhz clock (ttl compatible input) - this active high input enables both c2o and c2o outputs (pins 14 and 15). when low, these outputs are in high impedance condition. 17 20 ms3 mode select 3 input (ttl compatible) - this input in conjunction with ms2 (pin 7) selects the minor mode of operation for dpll #2. (refer to table 3.) 18, 19 21, 22 ai, bi inputs a and b (ttl compatible) - these are the two inputs of the uncommitted nand gate . 20 23 y o output y (totem pole output) - output of the uncommitted nand gate. 21 24 cvb variable clock bidirectional (ttl compatible input and totem-pole output) - when acting as an output (ms1-low) during the normal mode of dpll #1, this pin provides the 1.544 mhz clock locked to the input frame pulse f0i (pin 5). when ms1 is high, it is an input to an external clock at 1.544 mhz or 2.048 mhz to provide the internal signal at 8 khz to dpll #2. 22 26 cv variable clock (three state output) - this is the inverse output of the signal appearing on pin 21, the high impedance state of which is controlled by en cv (pin 1). 23 27 rst reset (schmitt trigger input) - this input (active low) puts the mt8941b in its reset state. to guarantee proper operation, the device must be reset after power-up. the time constant for a power-up reset circuit (see figures 9-13) must be a minimum of ?ve times the rise time of the power supply. in normal operation, the rst pin must be held low for a minimum of 60nsec to reset the device. 24 28 v dd v dd (+5v) power supply. 4, 5, 18, 25 nc no connection. pin description (continued) pin # name description dip plcc
mt8941b cmos 4 functional description the mt8941b is a dual digital phase-locked loop providing the timing and synchronization signals to the interface circuits for t1 and cept (30+2) primary multiplex digital transmission links. as shown in the functional block diagram (see figure 1), the mt8941b has two digital phase-locked loops (dplls), associated output controls and the mode selection logic circuits. the two dplls, although similar in principle, operate independently to provide t1 (1.544 mhz) and cept (2.048 mhz) transmission clocks and st-bus timing signals. the principle of operation behind the two dplls is shown in figure 3. a master clock is divided down to 8 khz where it is compared with the 8 khz input, and depending on the output of the phase comparison, the master clock frequency is corrected. figure 3 - dpll principle the mt8941b achieves the frequency correction in both directions by using three methods; speed-up, slow-down and no-correction. as shown in figure 4, the falling edge of the 8 khz input signal (c8kb for dpll #2 or f0i for dpll # 1) is used to sample the internally generated 8 khz clock and the correction signal (cs) once in every frame (125 m s). if the sampled cs is 1, then the dpll makes a speed-up or slow-down correction depending upon the sampled value of the internal 8 khz signal. a sampled 0 or 1 causes the frequency correction circuit to respectively stretch or shrink the master clock by half a period at one instant in the frame. if the sampled cs is 0, then the dpll makes no correction on the master clock input. note that since the internal 8 khz signal and the cs signal are derived from the master clock, a correction will cause both clocks to stretch or shrink simultaneously by an amount equal to half the period of the master clock. once in synchronization, the falling edge of the reference signal (c8kb or f0i) will be aligned with either the falling or the rising edge of cs. it is aligned with the rising edge of cs when the reference signal is slower than the internal 8 khz signal. on the other hand, the falling edge of the figure 4 - phase comparison reference signal will be aligned with the falling edge of cs if the reference signal is faster than the internal 8 khz signal. input-to-output phase relationship the no-correction window size is 324 ns for dpll #1 and 32 m s for dpll #2. it is possible for the relative phase of the reference signal to swing inside the no- correction window depending on its jitter and the relative drift of the master clock. as a result, the phase relationship between the input signal and the output clocks (and frame pulse in case of dpll #2) may vary up to a maximum of window size. this situation is illustrated in figure 4. the maximum phase variation for dpll #1 is 324 ns and for dpll #2 it is 32 m s. however, this phase difference can be absorbed by the input jitter buffer of mitels t1/cept devices. the no-correction window acts as a ?lter for low frequency jitter and wander since the dpll does not track the reference signal inside it. the size of the no-correction window is less than or equal to the size of the input jitter buffer on the t1 and cept devices to guarantee that no slip will occur in the received t1/cept frame. the circuit will remain in synchronization as long as the input frequency is within the lock-in range of the dplls (refer to the section on jitter performance and lock-in range for further details). the lock-in range is wide enough to meet the ccitt line rate speci?cation (1.544 mhz 32 ppm and 2.048 mhz 50 ppm) for the high capacity terrestrial digital service. the phase sampling is done once in a frame (8 khz) for each dpll. the divisions are set at 8 and 193 for dpll #1, which locks to the falling edge of the input master clock (12.352 mhz / 16.384 mhz) frequency correction ? 8 output (1.544 mhz / 2.048 mhz) input (8 khz) phase comparison ? 193 / ? 256 c8kb (dpll #2) or f0i (dpll #1) sampling edge interna l 8 khz correction correction cs speed-up region slow-down region t cs t csf no-correction f0b (dpll #2) dpll #1 : dpll #2: t csf = 766 t p16 where, t p12 is the 12.352 mhz master clock oscillator period for dpll #1 and t p16 is the 16.384 mhz master clock period for dpll #2. t cs = 4 t p12 0.5 t p12 t cs = 512 t p16 0.5 t p16
cmos mt8941b 5 at 8 khz to generate t1 (1.544 mhz) clock. for dpll #2, the divisions are set at 8 and 256 to provide the cept/st-bus clock at 2.048 mhz synchronized to the falling edge of the input signal (8 khz). the master clock source is speci?ed to be 12.352 mhz for dpll #1 and 16.384 mhz for dpll #2 over the entire temperature range of operation. the inputs ms0 to ms3 are used to select the operating mode of the mt8941b, see tables 1 to 4. all the outputs are controlled to the high impedance condition by their respective enable controls. the uncommitted nand gate is available for use in applications involving mitels mt8976/ mh89760 (t1 interfaces) and mt8979/mh89790 (cept interfaces). modes of operation the operation of the mt8941b is categorized into major modes and minor modes. the major modes are de?ned for both dplls by the mode select pins ms0 and ms1. the minor modes are selected by pins ms2 and ms3 and are applicable only to dpll #2. there are no minor modes for dpll #1. major modes of dpll #1 dpll #1 can be operated in three major modes as selected by ms0 and ms1 (table 1). when ms1 is low, it is in normal mode, which provides a t1 (1.544 mhz) clock signal locked to the falling edge of the input frame pulse f0i (8 khz). dpll #1 requires a master clock input of 12.352 mhz (c12i). in the second and third major modes (ms1 is high), dpll #1 is set to divide an external 1.544 mhz or 2.048 mhz signal applied at cvb (pin 21). the division can be set by ms0 to be either 193 (low) or 256 (high). in these modes, the 8 khz output at c8kb is connected internally to dpll #2, which operates in single clock mode. major modes of dpll #2 there are four major modes for dpll #2 selectable by ms0 and ms1, as shown in table 2. in all these modes dpll #2 provides the cept pcm30 timing, and the st-bus clock and framing signals. in normal mode, dpll #2 provides the cept/st- bus compatible timing signals locked to the falling edge of the 8 khz input signal (c8kb). these signals are 4.096 mhz (c4o and c4b) and 2.048 mhz (c2o and c2o) clocks, and the 8 khz frame pulse ( f0b) derived from the 16.384 mhz master clock. this mode can be the same as the free- run mode if the c8kb pin is tied to v dd or v ss . note: x: indicates dont care table 1. major modes of dpll #1 table 2. major modes of dpll #2 table 3. minor modes of dpll #2 in free-run mode, dpll #2 generates the stand- alone cept and st-bus timing and framing signals with no external inputs except the master clock set at 16.384 mhz. the dpll makes no correction in this con?guration and provides the timing signals without any jitter. m s 0 m s 1 mode of operation function x 0 normal provides the t1 (1.544 mhz) clock synchronized to the falling edge of the input frame pulse (f0i). 0 1 divide-1 dpll #1 divides the cvb input by 193. the divided output is connected to dpll #2. 1 1 divide-2 dpll #1 divides the cvb input by 256. the divided output is connected to dpll #2. m s 0 m s 1 mode of operation function 0 0 normal provides cept/st-bus timing signals locked to the falling edge of the 8 khz input signal at c8kb. 1 0 free-run provides cept/st-bus timing and framing signals with no external inputs, except the master clock. 01 single clock-1 provides cept/st-bus timing signals locked to the falling edge of the 8 khz internal signal provided by dpll #1. 11 single clock-2 provides cept/st-bus timing signals locked to the falling edge of the 8 khz internal signal provided by dpll #1. m s 2 m s 3 functional description 11 provides cept/st-bus 4.096 mhz and 2.048 mhz clocks and 8khz frame pulse depending on the major mode selected. 01 provides cept/st-bus 4.096 mhz & 2.048 mhz clocks depending on the major mode selected while f0b acts as an input. however, the input on f0b has no effect on the operation of dpll #2 unless it is in free-run mode. 00 overrides the major mode selected and accepts properly phase related external 4.096 mhz clock and 8 khz frame pulse to provide the st-bus compatible clock at 2.048 mhz. 10 overrides the major mode selected and accepts a 4.096 mhz external clock to provide the st-bus clock and frame pulse at 2.048 mhz and 8 khz, respectively.
mt8941b cmos 6 the operation of dpll #2 in single clock-1 mode is identical to single clock-2 mode, providing the cept and st-bus compatible timing signals synchro-nized to the internal 8 khz signal obtained from dpll#1 in divide mode. when single clock-1 mode is selected for dpll #2, it automatically selects the divide-1 mode for dpll #1, and thus, an external 1.544 mhz clock signal applied at cvb (pin 21) is divided by dpll #1 to generate the internal signal at 8 khz on to which dpll #2 locks. similarly when single clock-2 mode is selected, dpll #1 is in divide-2 mode, with an external signal of 2.048 mhz providing the internal 8 khz signal to dpll #2. in both these modes, this internal signal is available on c8kb (pin 10) and dpll #2 locks to the falling edge to provide the cept and st-bus compatible timing signals. this is in contrast to the normal mode where these timing signals are synchronized with the falling edge of the 8 khz signal on c8kb. minor modes of dpll #2 the minor modes for dpll #2 depends upon the status of the mode select bits ms2 and ms3 (pins 7 and 17). table 4. summary of modes of operation - dpll #1 and #2 mode # m s 0 m s 1 m s 2 m s 3 operating modes dpll #1 dpll #2 0 0000 normal mode: provides the t1 (1.544 mhz) clock synchronized to the falling edge of the input frame pulse ( f0i). properly phase related external 4.096 mhz clock and 8 khz frame pulse provide the st- bus clock at 2.048 mhz. 1 0 0 0 1 normal mode normal mode: f0b is an input but has no function in this mode. 2 0010 normal mode external 4.096 mhz provides the st-bus clock and frame pulse at 2.048 mhz and 8 khz, respectively. 3 0011 normal mode normal mode: provides the cept/st-bus compatible timing signals locked to the 8 khz input signal (c8kb). 4 0 1 0 0 divide-1 mode same as mode 0. 5 0 1 0 1 divide-1 mode single clock-1 mode f0b is an input but has no function in this mode. 6 0 1 1 0 divide-1 mode same as mode 2. 7 0111 divide-1 mode: divides the cvb input by 193. the divided output is connected to dpll #2. single clock-1 mode: provides the cept/st-bus compatible timing signals locked to the 8 khz internal signal provided by dpll #1. 8 1 0 0 0 normal mode same as mode 0. 9 1001 normal mode f0b is an input and dpll #2 locks on to it only if it is at 16 khz to provide the st-bus control signals. 10 1 0 1 0 normal mode same as mode 2. 11 1011 normal mode free-run mode: provides the st-bus timing signals with no external inputs except the master clock. 12 1 1 0 0 divide-2 mode same as mode 0. 13 1101 divide-2 mode single clock-2 mode: f0b is an input but has no function in this mode. 14 1 1 1 0 divide-2 mode same as mode 2. 15 1111 divide-2 mode: divides the cvb input by 256. the divided output is connected to dpll#2. single clock-2 mode: provides the cept/st-bus compatible timing signals locked to the 8 khz internal signal provided by dpll #1.
cmos mt8941b 7 when ms3 is high, dpll #2 operates in any of the major modes selected by ms0 and ms1. when ms3 is low, it overrides the major mode selected and dpll#2 accepts an external clock of 4.096 mhz on c4b (pin 13) to provide the 2.048 mhz clocks (c2o and c2o) and the 8 khz frame pulse ( f0b) compatible with the st-bus format. the mode select bit ms2 controls the direction of the signal on f0b (pin 6). when ms2 is low, the f0b pin is an 8 khz frame pulse input. this input is effective only when ms3 is also low and pin c4b is fed by a 4.096 mhz clock, which has a proper phase relationship with the signal on f0b (refer figure 18). otherwise, the input on pin f0b will have no bearing on the operation of dpll #2, unless it is in free-run mode as selected by ms0 and ms1. in free-run mode, the input on f0b is treated the same way as the c8kb input is in normal mode. the frequency of the signal on f0b should be 16 khz for dpll #2 to lock and generate the st-bus compatible clocks at 4.096 mhz and 2.048 mhz. when ms2 is high, the f0b pin provides the frame pulse output compatible with the st-bus format and locked to the internal or external input signal as determined by the other mode select pins. table 4 summarizes the modes of the two dpll. it should be noted that each of the major modes selected for dpll #2 can have any of the minor modes, although some of the combinations are table 5. functions of the bidirectional signals in each mode notes: i : input o : output x : dont care input. connect to v dd or v ss. functionally similar. the required operation of both dpll #1 and dpll #2 must be considered when determining ms0-ms3. the direction and frequency of each of the bidirectional signals are listed in table 5 for each of the given modes in table 4. jitter performance and lock-in range the output jitter of a dpll is composed of the intrinsic jitter, measured when no jitter is present at the input, and the output jitter resulting from jitter on the input signal. the spectrum of the intrinsic jitter for both dplls of the mt8941b is shown in figure 5. the typical peak-to-peak value for this jitter is 0.07ui. the transfer function, which is the ratio of the output jitter to the input jitter (both measured at a particular frequency), is shown in figure 6 for dpll #1 and figure 7 for dpll #2. the transfer function is measured when the peak-to-peak amplitude of the sinusoidal input jitter conforms to the following: 10 hz - 100 hz : 13.6 m s 100 hz - 10 khz : 20 db/decade roll-off > 10 khz : 97.2 ns the ability of a dpll to phase-lock the input signal to the reference signal and to remain locked depends upon its lock-in range. the lock-in range of the dpll is speci?ed in terms of the maximum frequency variation in the 8 khz reference signal. it is also directly affected by the oscillator frequency tolerance. table 6 lists different values for the lock-in range and the corresponding oscillator frequency tolerance for dpll #1 and dpll #2. the smaller the tolerance value, the larger the lock-in range. the t1 and cept standards specify that, for free running equipment, the output clock tolerance must be less than or equal to 32ppm and 50ppm respectively. this requirement restricts the table 6. lock-in range vs. oscillator frequency tolerance * please refer to the section on jitter performance and lock-in range for recommended oscillator tolerances for dpll #1 & #2. mode # f0b (khz) c4b (mhz) c8kb (khz) cvb (mhz) 0 i:8 i:4.096 i:x o:1.544 1 i:x o:4.096 i:8 o:1.544 2 o:8 i:4.096 i:x o:1.544 3 o:8 o:4.096 i:8 o:1.544 4 i:8 i:4.096 i:x i:1.544 5 i:x o:4.096 o:8 i:1.544 6 o:8 i:4.096 i:x i:1.544 7 o:8 o:4.096 o:8 i:1.544 8 i:8 i:4.096 i:x o:1.544 9 i:16 o:4.096 i:x o:1.544 10 o:8 i:4.096 i:x o:1.544 11 o:8 o:4.096 i:x o:1.544 12 i:8 i:4.096 i:x i:2.408 13 i:x o:4.096 o:8 i:2.408 14 o:8 i:4.096 i:x i:2.408 15 o:8 o:4.096 o:8 i:2.408 oscillator clock* tolerance ( ppm) lock-in range ( hz) dpll #1 dpll #2 5 2.55 1.91 10 2.51 1.87 20 2.43 1.79 32 2.33 1.69 50 2.19 1.55 100 1.79 1.15 150 1.39 .75 175 1.19 .55
mt8941b cmos 8 figure 5- the spectrum of the inherent jitter for either pll figure 6 - the jitter transfer function for pll1 figure 7 -the jitter transfer function for pll2
cmos mt8941b 9 oscillators of dpll #1 and dpll #2 to have maximum tolerances of 32ppm and 50ppm respectively. however, if dpll #1 and dpll #2 are daisy-chained as shown in figures 9 and 10, the output clock tolerance of dpll #1 will be equal to that of the dpll #2 oscillator when dpll #2 is free-running. in this case, the oscillator tolerance of dpll #1 has no impact on its output clock tolerance. for this reason, it is recommended to use a 32 ppm oscillator for dpll #2 and a 100 ppm oscillator for dpll #1. differences between mt8941b and mt8940 the mt8941b and mt8940 are pin and mode compatible for most applications. however, the user should take note of the following differences between the two parts. figure 8 - application differences between the mt8940 and mt8941b a) distributed timing m u x mt8940 mt8940 8 khz reference signal 8 khz reference signal line card 1 clocks line card n clocks data bus line card 1 line card n mt8941b m u x 8 khz reference signal 8 khz reference signal clocks b) centralized timing data bus
mt8941b cmos 10 besides the improved jitter performance, the mt8941b differs from the mt8940 in three other areas: 1. input pins on the mt8941b do not incorporate internal pull-up or pull-down resistors. in addition, the output con?guration of the bidirectional c8kb pin has been converted from an open drain output to a totem-pole output. 2. the mt8941b includes a no-correction window to ?lter out low frequency jitter and wander as illustrated in figure 4. consequently, there is no constant phase relationship between reference signal f0i of dpll # 1 or c8kb of dpll #2 and the output clocks of dpll #1 or dpll #2. figure 4 shows the new phase relationship between c8kb and the dpll #2 output clocks. figure 8 illustrates an application where the mt8941b cannot replace the mt8940 and suggests an alternative solution. 3. the mt8941b must be reset after power-up in order to guarantee proper operation, which is not the case for the mt8940. 4. for the mt8941b, dpll #2 locks to the falling edge of the c8kb reference signal. dpll#2 of the mt8940 locks on to the rising edge of c8kb. 5. while the mt8940 is available only in a 24 pin plastic dip, the mt8941b has an additional 28 pin plcc package option. applications the following ?gures illustrates how the mt8941b can be used in a minimum component count approach in providing the timing and synchro- nization signals for the mitel t1 or cept interfaces, and the st-bus. the hardware selectable modes and the independent control over each pll adds ?exibility to the interface circuits. it can be easily recon?gured to provide the timing and control signals for both the master and slave ends of the link. synchronization and timing signals for the t1 transmission link figures 9 and 10 show examples of how to generate the timing signals for the master and slave ends of a t1 link. at the master end of the link (figure 9), dpll #2 is the source of the st-bus signals derived from the crystal clock. the frame pulse output is looped back to dpll #1 (in normal mode), which locks to it to generate the t1 line clock. the timing relationship between the 1.544 mhz t1 clock and the 2.048 mhz st-bus clock meets the requirements of the mh89760/760b. the crystal clock at 12.352 mhz is used by dpll #1 to generate the 1.544 mhz clock, while dpll #2 (in free-run mode) uses the 16.384 mhz crystal oscillator to generate the st- bus clocks for system timing. the generated st- bus signals can be used to synchronize the system and the switching equipment at the master end. figure 9 - synchronization at the master end of the t1 transmission link crystal clock (16.384 mhz) crystal clock (12.352 mhz) mt8941b ms0 ms1 ms2 ms3 f0i c12i en cv c8kb c16i en c4o en c2o v ss v dd cvb c4b c2o f0b rst mh89760b c1.5i c2i f0i dsti dsto csti csto txt txr rxt rxr mt8980/81 st-bus switch t1 link (1.544 mbps) transmit receive mode of operation for the mt8941b dpll #1 - normal (ms0 = x; ms1 = 0) dpll #2 - free-run (ms0=1; ms2=1; ms3=1) v dd r c
cmos mt8941b 11 figure 10 - synchronization at the slave end of the t1 transmission link figure 11 - synchronization at the master end of the cept digital transmission link crystal clock (16.384 mhz) crystal clock (12.352 mhz) mt8941b ms0 ms1 ms2 ms3 f0i c12i en cv c8kb c16i en c4o en c2o v ss v dd cvb c4b c2o f0b rst mh89760b c1.5i c2i f0i dsti dsto csti csto txt txr rxt rxr mt8980/81 st-bus switch t1 link (1.544 mbps) transmit receive mode of operation for the mt8941b dpll #1 - normal ( ms1=0) dpll #2 - normal (ms0=0; ms1=0; ms2=1; ms3=1) v dd r c e8ko crystal clock (16.384 mhz) mt8941b ms0 ms1 ms2 ms3 f0i c12i en cv c8kb c16i en c4o en c2o v ss v dd c4b c2o f0b y o rst transmit receive mt8980/81 st-bus switch mh89790b c2i f0i dsti dsto csti0 csto rxt rxr mode of operation for the mt8941b dpll #1 - not used dpll #2 - free-run (ms0=1; ms1=0; ms2=1; ms3=1) csti1 outa outb v dd r c cept primary multiplex digital link at the slave end of the link (figure 10) both the dplls are in normal mode, with dpll #2 providing the st-bus timing signals locked to the 8 khz frame pulse (e8ko) extracted from the received signal on the t1 line. the regenerated frame pulse is looped back to dpll #1 to provide the t1 line clock, which is the same as the master end. the 12.352 mhz and 16.384 mhz crystal clock sources are necessary for dpll #1 and #2, respectively. synchronization and timing signals for the cept transmission link the mt8941b can be used to provide the timing and synchronization signals for the mh89790/790b, mitels cept (30+2) digital trunk interface hybrid. since the operational frequencies of the st-bus and the cept primary multiplex digital trunk are the same, only dpll #2 is required.
mt8941b cmos 12 figure 12 - synchronization at the slave end of the cept digital transmission link crystal clock (16.384 mhz) mt8941b ms0 ms1 ms2 ms3 f0i c12i en cv c8kb c16i en c4o en c2o v ss v dd c4b c2o f0b y o rst v dd r c mh89790b c2i f0i dsti dsto csti0 csto rxt rxr csti1 outa outb mt8980/81 st-bus switch transmit receive mode of operation for the mt8941b dpll #1 - not used dpll #2 - normal (ms0=0; ms1=0; ms2=1; ms3=1) cept primary multiplex digital link e8ko figures 11 and 12 show how the mt8941b can be used to synchronize the st-bus to the cept transmission link at the master and slave ends. generation of st-bus timing signals the mt8941b can source the properly formatted st- bus timing and control signals with no external inputs except the crystal clock. this can be used as the standard timing source for st-bus systems or any other system with similar clock requirements. figure 13 shows two such applications using dpll #2. in one case, the mt8941b is in free-run mode with an oscillator input of 16.384 mhz. in the other case, it is in normal mode with the c8kb input tied to v dd . for these applications, dpll #2 does not make any corrections and therefore, the output signals are free from jitter. dpll #1 is completely free. figure 13 - generation of the st-bus timing signals crystal clock (16.384 mhz) mt8941b ms0 ms1 ms2 ms3 f0i c12i en cv c8kb c16i en c4o en c2o ai bi v ss v dd c4b rst c4o c2o c2o f0b st-bus timing signals dpll #1 - not used dpll #2 - normal mode (ms0=0; ms1=0; ms2=1; ms3=1) v dd r c mt8941b ms0 ms1 ms2 ms3 f0i c12i en cv c8kb c16i en c4o en c2o ai bi v ss v dd c4b rst c4o c2o c2o f0b dpll #1 - not used dpll #2 - free-run mode (ms0=1; ms1=0;ms2=1; ms3=1) crystal clock (16.384 mhz) v dd r c st-bus timing signals
cmos mt8941b 13 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. absolute maximum ratings* - voltages are with respect to ground (v ss ) unless otherwise stated. parameter symbol min max units 1 supply voltage v dd -0.3 7.0 v 2 voltage on any pin v i v ss -0.3 v dd +0.3 v 3 input/output diode current i ik/ok 10 ma 4 output source or sink current i o 25 ma 5 dc supply or ground current i dd /i ss 50 ma 6 storage temperature t st -55 125 o c 7 package power dissipation plastic dip plcc p d p d 1200 600 mw mw recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 supply voltage v dd 4.5 5.0 5.5 v 2 input high voltage v ih 2.0 v dd v 3 input low voltage v il v ss 0.8 v 4 operating temperature t a -40 25 85 o c dc electrical characteristics - voltages are with respect to ground (v ss ) unless otherwise stated. v dd =5.0v 5%; v ss =0v; t a =-40 to 85 c. characteristics sym min typ ? max units test conditions 1 s u p supply current i dd 815ma under clocked condition, with the inputs tied to the same supply rail as the corresponding pull-up /down resistors. 2 i n input high voltage (for all the inputs except pin 23) v ih 2.0 v 3 positive-going threshold voltage (for pin 23) v + 3.0 4.0 v 4 input low voltage (for all the inputs except pin 23) v il 0.8 v 5 negative-going threshold voltage (for pin 23) v - 1.0 1.5 v 6 o u t output current high i oh -4 ma v oh =2.4 v 7 output current low i ol 4mav ol =0.4 v 8 leakage current on bidirect- ional pins and all inputs except c12i, c16i, rst, ms1, ms0 i il -100 -30 m a v in =v ss 9 leakage current on pins ms1, ms0 i il 35 120 m av in =v dd 10 leakage current on all three- state outputs and c12i, c16i, rst inputs i il -10 1 +10 m av i/o =v ss or v dd
mt8941b cmos 14 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 14 - timing information for dpll #1 in normal mode ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. (refer to figure 14) characteristics sym min typ ? max units test conditions 1 d p l l #1 cvb output (1.544 mhz) rise time t r1.5 6ns 85 pf load 2 cvb output (1.544 mhz) fall time t f1.5 6 ns 85 pf load 3 cvb output (1.544 mhz) clock period t p15 607 648 689 ns 4 cvb output (1.544 mhz) clock width (high) t w15h 318 324 ns 5 cvb output (1.544 mhz) clock width (low) t w15l 277 363 ns 6 cv delay (high to low) t 15hl 010ns 7 cv delay (low to high) t 15lh -7 3 ns ac electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. (refer to figure 15) characteristics sym min typ ? max units test conditions 1 d p l l #1 c8kb output (8khz) delay (high to high) t c8hh 0 10 25 ns 85 pf load 2 c8kb output (8 khz) delay (low to low ) t c8ll 13 34 ns 85 pf load 3 c8kb output duty cycle 66 50 % % in divide -1 mode in divide - 2 mode 4 inverted clock output delay (high to low ) t ichl 01025ns 5 inverted clock output delay (low to high) t iclh 0 7 18 ns cvb cv v oh v ol v oh v ol t f1.5 t 15hl t 15lh t r1.5 t p15 t w15h t w15l
cmos mt8941b 15 figure 15 - dpll #1 in divide mode figure 16 - timing information on dpll #2 outputs v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol f0b c4b c4o c2o c2o t fpl t fph t fc4 t rc4 t 4olh t 4ohl t 42lh t 42hl t fc2 t rc2 t 2olh t 2ohl t wfp t p2o t w2oh t w2ol t w4oh t w4ol t p4o cvb cv c8kb v ih v il v oh v ol v oh v ol t ichl t iclh t c8hh t c8ll
mt8941b cmos 16 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? -voltages are with respect to ground (v ss ) unless otherwise stated. (refer to figure 16) characteristics sym min typ ? max units test conditions 1 d p l l #2 c4b output clock period t p4o 213 244 275 ns 85 pf load 2 c4b output clock width (high) t w4oh 85 159 ns 3 c4b output clock width (low) t w4ol 116 122 ns 4 c4b output clock rise time t rc4 6 ns 85 pf load 5 c4b clock output fall time t fc4 6 ns 85 pf load 6 frame pulse output delay (high to low) from c4b t fpl 013ns 85 pf load 7 frame pulse output delay (low to high) from c4b t fph 08ns 85 pf load 8 frame pulse ( f0b) width t wfp 225 245 ns 9 c4o delay - low to high t 4olh 015ns 10 c4o delay - high to low t 4ohl 020ns 11 c4b to c2o delay (low to high) t 42lh 03ns 12 c4b to c2o delay (high to low) t 42hl 06ns 13 c2o clock period t p2o 457 488 519 ns 85 pf load 14 c2o clock width ( high ) t w2oh 207 280 ns 15 c2o clock width ( low ) t w2ol 238 244 ns 16 c2o clock rise time t rc2 6 ns 85 pf load 17 c2o clock fall time t fc2 6 ns 85 pf load 18 c2o delay - low to high t 2olh -5 2 ns 19 c2o delay - high to low t 2ohl 057ns
cmos mt8941b 17 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * please review the section on "jitter performance and lock-in range". figure 17 - master clock inputs ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 18 - external inputs on c4b and f0b for the dpll #2 ac electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. (refer to figure 14) characteristics sym min typ ? max units test conditions 1 c l o c k s master clocks input rise time t r 10 ns 2 master clocks input fall time t f 10 ns 3 master clock period (12.352mhz)* t p12 80.943 80.958 80.974 ns for dpll #1, while operating to provide the t1 clock signal. 4 master clock period (16.384mhz)* t p16 61.023 61.035 61.046 ns for dpll #2, while operating to provide the cept and st-bus timing signals. 5 duty cycle of master clocks 45 50 55 % 6 lock-in range dpll #1 dpll #2 -2.33 -1.69 +2.33 +1.69 hz with the master frequency tolerance at 32 ppm. ac electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. (refer to figure 18) characteristics sym min typ ? max units test conditions 1 f0b input pulse width (low) t wfp 244 ns 2 c4b input clock period t p4o 244 ns 3 frame pulse ( f0b) setup time t fs 50 ns 4 frame pulse ( f0b) hold time t fh 25 ns master clock inputs 2.4 v 1.5 v 0.4 v t r t f t p12 or t p16 f0b c4b v ih v il v ih v il t fs t wfp t fh t p4o
mt8941b cmos 18 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 19 - three state outputs and enable timings ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. (refer to figure 19) characteristics sym min typ ? max units test conditions 1 o u t p u t delay from enable to output (high to three state) t phz 16 ns 85 pf load 2 delay from enable to output (low to three state) t plz 12 ns 85 pf load 3 delay from enable to output (three state to high) t pzh 11 ns 85 pf load 4 delay from enable to output (three state to low) t pzl 50 16 ns 85 pf load ac electrical characteristics ? - uncommitted nand gate voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 propagation delay (low to high), input ai or bi to output t plh 11 ns 85 pf load 2 propagation delay (high to low), input ai or bi to output t phl 15 ns 85 pf load enable input output low to off output high to off 10% 90% 1.3 v 1.3 v outputs enabled outputs enabled outputs disabled t plz t phz t pzl t pzh t f 6 ns t r 6 ns 3.0 v 2.7 v 1.3 v 0.3 v
package outlines plastic j-lead chip carrier - p-suf?x f d 1 d h e 1 i a 1 a g d 2 e e 2 dim 20-pin 28-pin 44-pin 68-pin 84-pin min max min max min max min max min max a 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.200 (5.08) 0.165 (4.20) 0.200 (5.08) a 1 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.130 (3.30) 0.090 (2.29) 0.130 (3.30) d/e 0.385 (9.78) 0.395 (10.03) 0.485 (12.32) 0.495 (12.57) 0.685 (17.40) 0.695 (17.65) 0.985 (25.02) 0.995 (25.27) 1.185 (30.10) 1.195 (30.35) d 1 /e 1 0.350 (8.890) 0.356 (9.042) 0.450 (11.430) 0.456 (11.582) 0.650 (16.510) 0.656 (16.662) 0.950 (24.130) 0.958 (24.333) 1.150 (29.210) 1.158 (29.413) d 2 /e 2 0.290 (7.37) 0.330 (8.38) 0.390 (9.91) 0.430 (10.92) 0.590 (14.99) 0.630 (16.00) 0.890 (22.61) 0.930 (23.62) 1.090 (27.69) 1.130 (28.70) e 0 0.004 0 0.004 0 0.004 0 0.004 0 0.004 f 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) g 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) h 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) i 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) 4) for d & e add for allowable mold protrusion 0.010" e: (lead coplanarity) general-10
package outlines plastic dual-in-line packages (pdip) - e suf?x note: controlling dimensions in parenthesis ( ) are in millimeters. dim 8-pin 16-pin 18-pin 20-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) a 2 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) c 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356) d 0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) e 1 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) l 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) e b 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) e c 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b e c general-8
package outlines plastic dual-in-line packages (pdip) - e suf?x dim 22-pin 24-pin 28-pin 40-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35) a 2 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) c 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) d 1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) e 0.290 (7.37) .330 (8.38) e 1 0.330 (8.39) 0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) e 1 0.246 (6.25) 0.254 (6.45) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.400 bsc (10.16) 0.600 bsc (15.24) 0.600 bsc (15.24) 0.600 bsc (15.24) e a 0.300 bsc (7.62) e b 0.430 (10.92) l 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) a 15 15 15 15 e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b a shaded areas for 300 mil body width 24 pdip only
m mitel (design) and st-bus are registered trademarks of mitel corporation mitel semiconductor is an iso 9001 registered company copyright 1999 mitel corporation all rights reserved printed in canada technical documen t a tion - n o t for resale world headquarters - canada tel: +1 (613) 592 2122 fax: +1 (613) 592 6909 north america asia/paci?c europe, middle east, tel: +1 (770) 486 0194 tel: +65 333 6193 and africa (emea) fax: +1 (770) 631 8213 fax: +65 333 6192 tel: +44 (0) 1793 518528 fax: +44 (0) 1793 518581 http://www.mitelsemi.com information relating to products and services furnished herein by mitel corporation or its subsidiaries (collectively mitel) is believed to be reliable. however, mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by mitel or licensed from third parties by mitel, whatsoever. purchasers of products are also hereby noti?ed that the use of product in certain ways or in combination with mitel, or non-mitel furnished goods or services may infringe patents or other intellectual property rights owned by mitel. this publication is issued to provide information only and (unless agreed by mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, their speci?cations, services and other information appearing in this publication are subject to change by mitel without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speci?c piece of equipment. it is the users responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in signi?cant injury or death to the user. all products and materials are sold and services provided subject to mitels conditions of sale which are available on request.

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